"A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture."

Masao Taguchi et al. (1991)

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DOI: 10.1109/4.98963

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type: Journal Article

metadata version: 2025-02-26

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Masao Taguchi, Hiroyoshi Tomita, Toshiya Uchida, Yasuhiro Ohnishi, Kimiaki Sato, Taiji Ema, Masaaki Higashitani, Takashi Yabu:
A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture. IEEE J. Solid State Circuits 26(11): 1493-1497 (1991)

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