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"A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits."

Suguru Tachibana et al. (1995)

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DOI: 10.1109/4.375970

access: closed

type: Journal Article

metadata version: 2023-05-03

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  - https://dblp.org/rec/journals/jssc/TachibanaHTSYN95
Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome:
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits 30(4): 487-490 (1995)

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