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"A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune ..."

Toshikazu Suzuki et al. (2006)

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DOI: 10.1109/JSSC.2005.859029

access: closed

type: Journal Article

metadata version: 2024-05-07

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Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits 41(1): 152-160 (2006)

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