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ORCID"1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for ..."
Tomonori Sekiguchi et al. (2011)
- Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa:
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. IEEE J. Solid State Circuits 46(4): 828-837 (2011)
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