"A 209 K-transistor ECL gate array with RAM."

Hisayasu Sato et al. (1989)

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DOI: 10.1109/JSSC.1989.572595

access: closed

type: Journal Article

metadata version: 2024-11-12

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Hisayasu Sato, Takashi Nishimura, Makoto Tatsuki, Atsushi Ohba, Shiro Hine, Yoichi Kuramitsu:
A 209 K-transistor ECL gate array with RAM. IEEE J. Solid State Circuits 24(5): 1275-1279 (1989)

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