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"Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR ..."

Bodhisatwa Sadhu et al. (2013)

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DOI: 10.1109/JSSC.2013.2250457

access: closed

type: Journal Article

metadata version: 2022-06-23

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Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler, Ramesh Harjani:
Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS. IEEE J. Solid State Circuits 48(5): 1199-1211 (2013)

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