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"A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage ..."

Athanasios T. Ramkaj et al. (2020)

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DOI: 10.1109/JSSC.2019.2960476

access: closed

type: Journal Article

metadata version: 2021-02-09

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Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Marian Verhelst, Filip Tavernier:
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. IEEE J. Solid State Circuits 55(6): 1553-1564 (2020)

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