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"A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique."

Yusuke Okaniwa et al. (2005)

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DOI: 10.1109/JSSC.2005.852014

access: closed

type: Journal Article

metadata version: 2022-03-02

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  - https://dblp.org/rec/journals/jssc/OkaniwaTKYCOTWK05
Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40(8): 1680-1687 (2005)

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