"A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit ..."

Yasumasa Nishimura et al. (1989)

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DOI: 10.1109/4.16300

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type: Journal Article

metadata version: 2024-11-12

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Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima:
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. IEEE J. Solid State Circuits 24(1): 43-49 (1989)

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