Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Automated Hierarchical Cmos Analog Circuit Stack Generation with ..."

Ravindranath Naiknaware, Terri S. Fiez (1999)

> Home

Details and statistics

DOI: 10.1109/JSSC.1999.748181

access: closed

type: Journal Article

metadata version: 2022-07-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/NaiknawareF99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/NaiknawareF99
Ravindranath Naiknaware, Terri S. Fiez:
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. IEEE J. Solid State Circuits 34(3): 304-303 (1999)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.