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ORCID"A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy ..."
Hiroyuki Mizuno et al. (1996)
- Hiroyuki Mizuno
, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure:
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31(11): 1618-1624 (1996)
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