Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID"A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM."
Thomas H. Lee et al. (1994)
- Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa:
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM. IEEE J. Solid State Circuits 29(12): 1491-1496 (1994)
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2023-05-03 22:43 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
