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"A low-power 16×16-b parallel multiplier utilizing pass-transistor logic."

Chong-Fatt Law, Samir S. Rofail, Kiat Seng Yeo (1999)

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DOI: 10.1109/4.792613

access: closed

type: Journal Article

metadata version: 2023-06-26

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Chong-Fatt Law, Samir S. Rofail, Kiat Seng Yeo:
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. IEEE J. Solid State Circuits 34(10): 1395-1399 (1999)

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