"A 10-gb/s CMOS clock and data recovery circuit with an analog phase ..."

Rainer Kreienkamp et al. (2005)

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DOI: 10.1109/JSSC.2005.843624

access: closed

type: Journal Article

metadata version: 2022-03-02

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Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff:
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. IEEE J. Solid State Circuits 40(3): 736-743 (2005)

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