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"A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface."

Changhyun Kim et al. (1999)

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DOI: 10.1109/4.760374

access: closed

type: Journal Article

metadata version: 2022-07-06

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  - https://dblp.org/rec/journals/jssc/KimKJKMCYCHPHCC99
Changhyun Kim, Kye-Hyun Kyung, W.-P. Jeong, J.-S. Kim, Byung-Sik Moon, Joon-Wan Chai, S.-M. Yim, Jung-Hwan Choi, K.-H. Han, C.-J. Park, Hong-Sun Hwang, H. Choi, Sung-Burn Cho, Clemenz L. Portmann, Soo-In Cho:
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. IEEE J. Solid State Circuits 34(5): 645-652 (1999)

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