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"A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking ..."
Jihyo Kang et al. (2022)
- Jihyo Kang
, Jaehyeok Yang
, Kyunghoon Kim, Joo-Hyung Chae
, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim
, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang
, Sangkwon Lee
, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha:
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57(1): 212-223 (2022)
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