Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates."

Masato Iwabuchi et al. (1994)

> Home

Details and statistics

DOI: 10.1109/4.280690

access: closed

type: Journal Article

metadata version: 2023-05-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/IwabuchiUKOMHHN94
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/IwabuchiUKOMHHN94
Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima:
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits 29(4): 419-425 (1994)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.