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"A Highly Digital MDLL-Based Clock Multiplier That Leverages a ..."
Belal Helal et al. (2008)
- Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott:
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. IEEE J. Solid State Circuits 43(4): 855-863 (2008)
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