"An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC ..."

Tetsutaro Hashimoto et al. (2018)

> Home

Details and statistics

DOI: 10.1109/JSSC.2017.2777101

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/HashimotoKHKTSN18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/HashimotoKHKTSN18
Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita:
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. IEEE J. Solid State Circuits 53(4): 1028-1037 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.