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"A background optimization method for PLL by measuring phase jitter ..."

Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa (2005)

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DOI: 10.1109/JSSC.2005.845556

access: closed

type: Journal Article

metadata version: 2022-03-02

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Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa:
A background optimization method for PLL by measuring phase jitter performance. IEEE J. Solid State Circuits 40(4): 941-950 (2005)

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