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"A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop ..."

Kun-Yung Ken Chang et al. (2003)

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DOI: 10.1109/JSSC.2003.810045

access: closed

type: Journal Article

metadata version: 2022-07-05

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Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos:
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE J. Solid State Circuits 38(5): 747-754 (2003)

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