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"A 130-nm triple-Vt 9-MB third-level on-die cache for the ..."

Jonathan Chang et al. (2005)

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DOI: 10.1109/JSSC.2004.837970

access: closed

type: Journal Article

metadata version: 2022-03-14

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Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni:
A 130-nm triple-V_t 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. IEEE J. Solid State Circuits 40(1): 195-203 (2005)

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