"A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture."

Yasuro Shobatake et al. (1991)

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DOI: 10.1109/49.105171

access: closed

type: Journal Article

metadata version: 2020-04-02

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  - https://dblp.org/rec/journals/jsac/ShobatakeMSKSNS91
Yasuro Shobatake, Masahiko Motoyama, Emiko Shobatake, Takashi Kamitake, Shoichi Shimizu, Makoto Noda, Kenji Sakaue:
A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture. IEEE J. Sel. Areas Commun. 9(8): 1248-1254 (1991)

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