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"The logic design language and verification environment for the VLSI-/370."

Wolfgang Roesner (1988)

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DOI: 10.1016/0165-6074(88)90025-7

access: closed

type: Journal Article

metadata version: 2022-08-05

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  - https://dblp.org/rec/journals/jsa/Roesner88
Wolfgang Roesner:
The logic design language and verification environment for the VLSI-/370. Microprocess. Microprogramming 24(1-5): 35-42 (1988)

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