"Fault and test-process modelling for integrated circuits."

Juraj Povazanec, Vladislav Musil (1997)

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type: Journal Article

metadata version: 2020-05-19

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Juraj Povazanec, Vladislav Musil:
Fault and test-process modelling for integrated circuits. J. Syst. Archit. 43(1-5): 123-127 (1997)

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