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"Verification and validation of hierarchical CMOS gate array layouts."

Michael Payer (1987)

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DOI: 10.1016/0165-6074(87)90076-7

access: closed

type: Journal Article

metadata version: 2022-08-05

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Michael Payer:
Verification and validation of hierarchical CMOS gate array layouts. Microprocess. Microprogramming 21(1-5): 445-452 (1987)

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