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"System performance evaluation by combining RTC and VHDL simulation: A case ..."

Godofredo R. Garay et al. (2013)

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DOI: 10.1016/J.SYSARC.2013.09.006

access: closed

type: Journal Article

metadata version: 2020-06-10

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  - https://dblp.org/rec/journals/jsa/GarayODCA13
Godofredo R. Garay, Julio Ortega Lopera, Antonio F. Díaz, Luis Corrales, Vicente Alarcón Aquino:
System performance evaluation by combining RTC and VHDL simulation: A case study on NICs. J. Syst. Archit. 59(10-D): 1277-1298 (2013)

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