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"Speed-area-power optimization for DCFL and SDCFL class of logic using ring ..."

K. Eshraghian et al. (1991)

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DOI: 10.1016/0165-6074(91)90326-O

access: closed

type: Journal Article

metadata version: 2022-10-20

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  - https://dblp.org/rec/journals/jsa/EshraghianSCN91
K. Eshraghian, Roberto Sarmiento, Pedro P. Carballo, Antonio Núñez:
Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation. Microprocessing and Microprogramming 32(1-5): 75-82 (1991)

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