"A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip."

Paul J. Murtagh, Ah Chung Tsoi (1997)

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DOI: 10.1006/JPDC.1997.1343

access: closed

type: Journal Article

metadata version: 2023-08-19

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Paul J. Murtagh, Ah Chung Tsoi:
A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip. J. Parallel Distributed Comput. 44(1): 53-70 (1997)

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