"A pipelined-loop-compatible architecture and algorithm to reduce ..."

Gerald R. Morris, Viktor K. Prasanna (2008)

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DOI: 10.1016/J.JPDC.2008.03.004

access: closed

type: Journal Article

metadata version: 2020-02-22

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Gerald R. Morris, Viktor K. Prasanna:
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer. J. Parallel Distributed Comput. 68(7): 913-921 (2008)

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