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"Probability-Based Optimal Sizing of Power-Gating Transistors in Full ..."

Pradeep S. Nair, Savithra Eratne, Eugene B. John (2012)

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DOI: 10.1166/JOLPE.2012.1207

access: closed

type: Journal Article

metadata version: 2021-10-14

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  - https://dblp.org/rec/journals/jolpe/NairEJ12
Pradeep S. Nair, Savithra Eratne, Eugene B. John:
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. J. Low Power Electron. 8(4): 464-471 (2012)

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