"A VLSI Design Design-Synthesis Methodology at the transistor Layout Level."

Nikolaos G. Bourbakis, Mohammad Mortazavi (2005)

> Home

Details and statistics

DOI: —

access: closed

type: Journal Article

metadata version: 2020-05-14

- view
  - electronic edition @ iospress.com
- export record
  dblp key:
  - journals/jid/BourbakisM05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jid/BourbakisM05
Nikolaos G. Bourbakis, Mohammad Mortazavi:
A VLSI Design Design-Synthesis Methodology at the transistor Layout Level. Trans. SDPS 9(3): 63-85 (2005)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.