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"Reliability improvement of logic and clock paths in power-efficient designs."

Senthil Arasu et al. (2014)

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DOI: 10.1145/2543749.2543751

access: closed

type: Journal Article

metadata version: 2020-06-08

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  - journals/jetc/ArasuNRCKC14
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  - https://dblp.org/rec/journals/jetc/ArasuNRCKC14
Senthil Arasu, Mehrdad Nourani, Vijay Reddy, John M. Carulli Jr., Gautam Kapila, Min Chen:
Reliability improvement of logic and clock paths in power-efficient designs. ACM J. Emerg. Technol. Comput. Syst. 10(1): 3:1-3:23 (2014)

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