"Min-rank conjecture for log-depth circuits."

Stasys Jukna, Georg Schnitger (2011)

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DOI: 10.1016/J.JCSS.2009.09.003

access: open

type: Journal Article

metadata version: 2025-01-19

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Stasys Jukna, Georg Schnitger:
Min-rank conjecture for log-depth circuits. J. Comput. Syst. Sci. 77(6): 1023-1038 (2011)

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