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"Design and Performance of High-Speed Energy-Efficient CMOS Double Tail ..."

Vikrant Varshney, Avaneesh K. Dubey, Rajendra Kumar Nagaria (2021)

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DOI: 10.1142/S0218126621501917

access: closed

type: Journal Article

metadata version: 2023-03-18

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  - https://dblp.org/rec/journals/jcsc/VarshneyDN21
Vikrant Varshney, Avaneesh K. Dubey, Rajendra Kumar Nagaria:
Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications. J. Circuits Syst. Comput. 30(11): 2150191:1-2150191:22 (2021)

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