Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Iterative and Fully Pipelined High Throughput Efficient Architectures of ..."

Vijay Kumar Sharma, Saurabh Kumar, Kamala Kanta Mahapatra (2016)

> Home

Details and statistics

DOI: 10.1142/S0218126616500493

access: closed

type: Journal Article

metadata version: 2020-10-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/SharmaKM16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/SharmaKM16
Vijay Kumar Sharma, Saurabh Kumar, Kamala Kanta Mahapatra:
Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC. J. Circuits Syst. Comput. 25(5): 1650049:1-1650049:29 (2016)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.