Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic ..."

M. C. Parameshwara, H. C. Srinivasaiah (2017)

> Home

Details and statistics

DOI: 10.1142/S0218126617500141

access: closed

type: Journal Article

metadata version: 2020-08-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/ParameshwaraS17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/ParameshwaraS17
M. C. Parameshwara, H. C. Srinivasaiah:
Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. J. Circuits Syst. Comput. 26(1): 1750014:1-1750014:15 (2017)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.