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"Power-Delay-Error-Efficient Approximate Adder for Error-Resilient ..."

Vinay Kumar et al. (2019)

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DOI: 10.1142/S0218126619501718

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - https://dblp.org/rec/journals/jcsc/KumarSUK19
Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar:
Power-Delay-Error-Efficient Approximate Adder for Error-Resilient Applications. J. Circuits Syst. Comput. 28(10): 1950171:1-1950171:14 (2019)

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