"Low-Power and Area-Efficient Parallel Multiplier Design Using ..."

Pankaj Kumar, Rajender Kumar Sharma (2017)

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DOI: 10.1142/S021812661750030X

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type: Journal Article

metadata version: 2020-08-25

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Pankaj Kumar, Rajender Kumar Sharma:
Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing. J. Circuits Syst. Comput. 26(2): 1750030:1-1750030:18 (2017)

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