"Power gating Technique using FinFET for Minimization of sub-Threshold ..."

K. Keerti Kumar, N. Bheema Rao (2014)

> Home

Details and statistics

DOI: 10.1142/S0218126614501096

access: closed

type: Journal Article

metadata version: 2020-08-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/KumarR14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/KumarR14
K. Keerti Kumar, N. Bheema Rao:
Power gating Technique using FinFET for Minimization of sub-Threshold Leakage Current. J. Circuits Syst. Comput. 23(8) (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.