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"An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 ..."

Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh (2012)

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DOI: 10.1142/S0218126612400257

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - journals/jcsc/ChengWY12
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  - https://dblp.org/rec/journals/jcsc/ChengWY12
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh:
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology. J. Circuits Syst. Comput. 21(8) (2012)

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