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"A SAT-Based Methodology for Effective Clock Gating for Power Minimization."
Khushbu Chandrakar, Suchismita Roy (2019)
- Khushbu Chandrakar, Suchismita Roy:
A SAT-Based Methodology for Effective Clock Gating for Power Minimization. J. Circuits Syst. Comput. 28(1): 1950011:1-1950011:17 (2019)
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