"Combining Software and Hardware Test Generation Methods to Verify VHDL Models."

Vacius Jusas, Tomas Neverdauskas (2013)

> Home

Details and statistics

DOI: 10.5755/J01.ITC.42.4.4261

access: open

type: Journal Article

metadata version: 2023-03-21

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/itc/JusasN13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/itc/JusasN13
Vacius Jusas, Tomas Neverdauskas:
Combining Software and Hardware Test Generation Methods to Verify VHDL Models. Inf. Technol. Control. 42(4): 362-368 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.