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"An improved reconfigurable logic in resistive random access memory."

Yi Zhao et al. (2022)

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DOI: 10.1016/J.VLSI.2022.07.005

access: closed

type: Journal Article

metadata version: 2024-08-07

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  - journals/integration/ZhaoCLWL22
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  - https://dblp.org/rec/journals/integration/ZhaoCLWL22
Yi Zhao, Hui Chen, Peng Liu, Jigang Wu, Dongxiang Luo:
An improved reconfigurable logic in resistive random access memory. Integr. 87: 169-175 (2022)

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