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"Reconfigurable very high throughput low latency VLSI (FPGA) design ..."
Jubin Mitra, Tapan Kumar Nayak (2017)
- Jubin Mitra, Tapan Kumar Nayak:
Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32. Integr. 56: 1-14 (2017)
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