"Gate-level dual-threshold static power optimization methodology (GDSPOM) ..."

B. Chung, J. B. Kuo (2008)

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DOI: 10.1016/J.VLSI.2007.03.001

access: closed

type: Journal Article

metadata version: 2020-02-20

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B. Chung, J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. Integr. 41(1): 9-16 (2008)

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