"Low-power and high-speed SRAM cells for double-node-upset recovery."

Shuo Cai et al. (2023)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2023.02.010

access: closed

type: Journal Article

metadata version: 2023-06-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/CaiWXW023
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/CaiWXW023
Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu:
Low-power and high-speed SRAM cells for double-node-upset recovery. Integr. 91: 1-9 (2023)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.