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"A novel test compression algorithm for analog circuits to decrease ..."

Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan (2017)

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DOI: 10.1016/J.VLSI.2016.10.010

access: closed

type: Journal Article

metadata version: 2020-02-20

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Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
A novel test compression algorithm for analog circuits to decrease production costs. Integr. 58: 538-548 (2017)

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