"An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation."

Yoshinobu Higami et al. (2009)

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DOI: 10.11185/IMT.4.727

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type: Journal Article

metadata version: 2024-09-05

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Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. Inf. Media Technol. 4(4): 727-739 (2009)

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