"FPGA-based parallel architecture for PID control algorithm and HDL ..."

T. Ananthan, M. V. Vaidyan (2013)

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DOI: 10.1504/IJES.2013.057703

access: closed

type: Journal Article

metadata version: 2020-09-11

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T. Ananthan, M. V. Vaidyan:
FPGA-based parallel architecture for PID control algorithm and HDL co-simulation. Int. J. Embed. Syst. 5(4): 239-247 (2013)

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